Junction-Isolated Electrical Test Structures for Critical Dimension Calibration Standards

Published

May 1, 2004

Author(s)

Richard A. Allen, Michael W. Cresswell, Loren W. Linholm

Abstract

NIST is developing single-crystal reference materials for use as critical dimension (CD) calibration standards. In earlier work, these structures have been electrically isolated from the substrate by the buried insulator of a silicon-on-insulator (SOI) wafer. This paper describes a new method of isolating the structures from the substrate by means of a pn junction. The junction isolation technique is expected to provide several advantages over the SOI technique including minimal susceptibility to charging when imaged in a CD scanning electron microscope (CDSEM), better edge quality, and ease of manufacture. Primary calibration of these reference materials is via imaging the cross-section of the feature with high-resolution transmission electron microscopy (HRTEM) at sufficient magnification to resolve and count the individual lattice planes while electrical test structure metrology techniques provide the transfer calibration. Secondary calibration is performed via electrical test structure metrology, supplemented by visual techniques to verify that the features meet uniformity requirements. In this paper, we describe results for determining the electrical critical dimensions of these junction-isolated structures. This measurement and data analysis technique is a unique combination of the short-bridge variation of the cross-bridge resistor and the multi-bridge structure.

Citation

IEEE Transactions on Semiconductor Manufacturing

Volume

17

Issue

2

Pub Type

Journals

Keywords

anisotropic etch, critical dimension, electrical test structure, linewidth

Citation

Allen, R. , Cresswell, M. and Linholm, L. (2004), Junction-Isolated Electrical Test Structures for Critical Dimension Calibration Standards, IEEE Transactions on Semiconductor Manufacturing (Accessed May 23, 2025)