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Introduction: Characterization and Metrology for Nanoelectronics and Nanostructures

Published

Author(s)

Zhiyong Ma, David G. Seiler

Abstract

Continued Moore's law scaling and miniaturization of low power semiconductor chips with ever increasing functionality in the past decade have been relentlessly driving research and development of new devices, materials, and process capabilities to meet performance, power and cost requirement. The evaluation and development of these new technology capabilities are alternately challenging and pushing the limits of existing characterization and metrology techniques and are fueling numerous innovations and advances across the metrology industry, measurement community, and academia in this field. As CMOS transistor scaling and interconnect RC scaling reach their respective physics and/or material limitations, some fundamental changes in alternative materials, device architecture, and process integration schemes are being considered and explored to extend CMOS technology to its ultimate limits.
Citation
Characterization and Metrology for Nanoelectronics and Nanostructures
Publisher Info
Pan Stanford, Singapore, -1

Citation

Ma, Z. and Seiler, D. (2016), Introduction: Characterization and Metrology for Nanoelectronics and Nanostructures, Characterization and Metrology for Nanoelectronics and Nanostructures, Pan Stanford, Singapore, -1 (Accessed April 21, 2024)
Created September 22, 2016, Updated October 12, 2021