Schafft, H.
(1999),
Interconnect Reliability Test Chip NIST 36: For Development of Measurement Tools & Standards, 1998 IEEE International Integrated Reliability Workshop Final Report, Lake Tahoe, CA
(Accessed December 5, 2024)
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Interconnect Reliability Test Chip NIST 36: For Development of Measurement Tools & Standards
Published
Author(s)
Abstract
NIST 36 is a collection of interconnect reliability test structures designed by NIST in collaboration with members of JEDEC Committee JC14.2 on Wafer Level Reliability and with industry researchers. It is a vehicle for improving existing reliability standards and for developing new ones for interconnects that are based on the results of interlaboratory and other experiments. These experiments are being coordinated through JEDEC Committee JC14.2. The United Microelectronics Corporation of Taiwan, R.O.C., plays a vital role by having volunteered to fabricate NIST 36 using their 0.35 micron back-end process that uses a layered Al-Cu metallization and tungsten plugs.Proceedings Title
1998 IEEE International Integrated Reliability Workshop Final Report
Conference Dates
October 12-15, 1998
Conference Location
Lake Tahoe, CA
Pub Type
Conferences
Keywords
electromigration, interconnects, isothermal test, reliability, standards, sweat test, test structures
Citation
Issues
If you have any questions about this publication or are having problems accessing it, please contact reflib@nist.gov.
Created December 31, 1999, Updated February 17, 2017