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Impact of BTI on Random Logic Circuit Critical Timing

Published

Author(s)

Kin P. Cheung, Jiwu Lu, Guangfan Jiao, Jason P. Campbell, Jason T. Ryan

Abstract

Bias temperature instability (BTI) is known to be a serious reliability issue for state-of-the-art Silicon MOSFET technology [1-6]. It is well-known that in addition to a “permanent” degradation, there is a large recoverable degradation component [7] that gets larger as the delay between stress and measure is shorter. This recoverable component, when it is taken into account, is often treated as a source for lifetime extension [1-6, 8-12]. In other words, the recovery buys margin in measured lifetime. BTI degradations mostly manifest as threshold voltage (VTH) increase, leading to frequency degradation in ring-oscillator (RO) “test” circuits [8-12]. This RO degradation is the most “circuit relevant” BTI guidance for circuit designers even though RO patterns are poor representations of random digital logic. The fact that recovery is time sensitive leads one to ask, naturally, what will happen to the random pattern in a real logic circuit? To answer this question, existing experimental techniques are not adequate. We recently developed a single transistor eye-diagram technique to address this question and found a previously overlooked but serious BTI impact on critical timing of random logic circuits [13, 14].
Proceedings Title
2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology
Conference Dates
October 28-31, 2014
Conference Location
Guilin

Keywords

BTI, Jitter, Random Logic

Citation

Cheung, K. , Lu, J. , Jiao, G. , Campbell, J. and Ryan, J. (2014), Impact of BTI on Random Logic Circuit Critical Timing, 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, Guilin, -1, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=917272 (Accessed August 8, 2022)
Created October 31, 2014, Updated February 19, 2017