Hardware Security Failure Scenarios

Published

November 13, 2024

Author(s)

Peter Mell, Irena Bojanova

Abstract

Historically, hardware has been assumed to be inherently secure. However, chips are both created with software and contain complex encodings (e.g., circuit designs and firmware). This leads to bugs, some of which compromise security. This publication evaluates the types of vulnerabilities that can occur and leverages existing work on hardware weaknesses. For each type, a security failure scenario is provided that describes how the weakness could be exploited, where the weakness typically occurs, and what kind of damage could be done by an attacker. The 98 failure scenarios provided demonstrate the extensive and broadly distributed possibilities for hardware-related security failures.

Citation

NIST Interagency/Internal Report (NISTIR) - 8517

Report Number

8517

NIST Pub Series

NIST Interagency/Internal Report (NISTIR)

Pub Type

NIST Pubs

Download Paper

https://doi.org/10.6028/NIST.IR.8517

Local Download

Keywords

chips, circuit logic, code, design, failures, firmware, hardware, scenarios, security, vulnerability, weakness

Citation

Mell, P. and Bojanova, I. (2024), Hardware Security Failure Scenarios, NIST Interagency/Internal Report (NISTIR), National Institute of Standards and Technology, Gaithersburg, MD, [online], https://doi.org/10.6028/NIST.IR.8517, https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=958868 (Accessed October 13, 2025)