Evaluation of New In-Chip and Arrayed Line Overlay

Published

May 1, 2004

Author(s)

Ravikiran Attota, Richard M. Silver, M R. Bishop, Egon Marx, Jay S. Jun, Michael T. Stocker, M P. Davidson, Robert D. Larrabee

Abstract

Two types of overlay targets have been designed and evaluated for the study of optical overlay metrology. They are in-chip and arrayed overlay targets. In-chip targets are three-bar two-level targets designed to be placed in or near the active device area of a chip. They occupy a small area in the range of 5 ¿m2 to 15 ¿m2 and have line widths, which are nominally device dimensions. The close proximity of the line features result in strong proximity effects. We have used two well-established theoretical models to simulate and study the effects of proximity on overlay measurements. In this paper, we also present a comparison of optical overlay results with scanning electron microscope measurements. Arrayed targets have also been designed to improve and enhance the optical signal for small critical dimension features. We have also compared theoretical simulations of arrayed targets to experimental results. In these comparisons we observe a significant variation in the location of the best focus image with respect to the features. The through-focus focus-metric we have implemented in the current work to determine the best focus image shows interesting properties with potential applications for line width metrology and process control. Based on simulation results, the focus-metric is sensitive to changes in line width dimensions on the nanometer scale.

Proceedings Title

Proceedings of SPIE, Metrology, Inspection, and Process Control for Microlithography XVIII, Richard M. Silver, Editor

Volume

5375

Conference Dates

February 23, 2004

Conference Location

Santa Clara, CA, USA

Conference Title

Overlay and Registration Metrology II

Pub Type

Conferences

Citation

Attota, R. , Silver, R. , Bishop, M. , Marx, E. , Jun, J. , Stocker, M. , Davidson, M. and Larrabee, R. (2004), Evaluation of New In-Chip and Arrayed Line Overlay, Proceedings of SPIE, Metrology, Inspection, and Process Control for Microlithography XVIII, Richard M. Silver, Editor, Santa Clara, CA, USA (Accessed October 9, 2025)