Effect of device design on charge offset drift in Si/SiO2 single electron devices

Published

October 9, 2018

Author(s)

Binhui Hu, Erick Ochoa, Daniel Sanchez, Justin K. Perron, Neil M. Zimmerman, Michael Stewart

Abstract

We have measured the low-frequency time instability known as charge offset drift of Si/SiO2 single electron devices (SEDs) with and without an overall poly-Si top gate. We find that SEDs with a poly-Si top gate have significantly less charge offset drift, exhibiting fewer isolated jumps and a factor of two reduction in fluctuations about a stable mean value. The observed reduction can be accounted for by the electrostatic reduction in the mutual capacitance between defects and the quantum dot, and increase in the defect total capacitance. These results depart from the accepted understanding that the level of charge offset drift in SEDs is determined by the intrinsic material properties, forcing consideration of the device design as well. We expect these results to be of importance in developing SEDs for applications from quantum information to metrology or wherever charge noise or integrability of devices is a challenge.

Citation

Journal of Applied Physics

Volume

124

Issue

14

Pub Type

Journals

Download Paper

https://doi.org/10.1063/1.5048013

Local Download

Keywords

single-electron device, quantum dot, noise, stability, silicon

Citation

Hu, B. , Ochoa, E. , Sanchez, D. , Perron, J. , Zimmerman, N. and Stewart, M. (2018), Effect of device design on charge offset drift in Si/SiO2 single electron devices, Journal of Applied Physics, [online], https://doi.org/10.1063/1.5048013, https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=926169 (Accessed April 26, 2024)