Diffusion Barrier Cladding in Si/SiGe Resonant Interband Tunneling Diodes and Their Patterned Growth on PMOS Source/Drain Regions

Published

January 1, 2003

Author(s)

N Jin, A T. Rice, P R. Berger, P E. Thompson, C Rivas, R Lake, S Sudirgo, J J. Kempisty, B Curanovic, S L. Rommel, K D. Hirschman, S K. Kurinec, P Chi, David S. Simons, S.J. Chung

Abstract

Si/SiGe resonant interband tunnel diodes (RITD) employing delta-doping spikes that demonstrate negative differential resistance (NDR) at room temperature are presented. Efforts have focused on improving the tunnel diode peak-to-valley current ratio (PVCR) figure-of-merit, as well as address issues of manufacturability and CMOS integration. Thin SiGe layers sandwiching the B d-doping spike used to suppress B out-diffusion are discussed. A room temperature PVCR of 3.6 was measured with a peak current density of 0.3 kA/cm2. Results clearly show that, by introducing SiGe layers to clad the B delta-doping layer, the B diffusion is suppressed during the post-growth annealing, which raises the thermal budget. A higher RTA temperature appears to be more effective in eliminating defects and results in a lower valley current and higher PVCR. RITDs grown by selective area molecular beam epitaxy have been realized inside of low temperature oxide openings, with performance comparable to RITDs grown on bulk substrates.

Citation

IEEE Transactions on Electron Devices

Pub Type

Journals

Keywords

delta-doping, molecular beam epitaxy, SiGe

Citation

Jin, N. , Rice, A. , Berger, P. , Thompson, P. , Rivas, C. , Lake, R. , Sudirgo, S. , Kempisty, J. , Curanovic, B. , Rommel, S. , Hirschman, K. , Kurinec, S. , Chi, P. , Simons, D. and Chung, S. (2003), Diffusion Barrier Cladding in Si/SiGe Resonant Interband Tunneling Diodes and Their Patterned Growth on PMOS Source/Drain Regions, IEEE Transactions on Electron Devices (Accessed October 10, 2024)