There are a number of factors driving 3D integration including reduced power consumption, RC delay, and form factor as well as increased bandwidth. However, before these advantages can be realized, various technical and cost hurdles must be overcome. One of the critical process steps in all 3D processes is stacking, which may take the form of wafer-to-wafer, chip-to-wafer, or chip-to-chip bonding. This bonding may be temporary, such as is used for attaching a device wafer to a handle wafer for thinning or permanent, incorporating direct metal bonds or solder bumps to carry signals between the wafers and oxide bonds or underfill in the regions without conductors. In each of these processes it is critical that the bonding is executed in such a way as to prevent the occurrence of voids between the layers. This paper describes the capabilities of infrared (IR) microscopy to detect micrometer size voids that are formed in the lamination interface between wafers. The infrared microscope is described and measurement results from a bonded void wafer set are included. The wafers used include programmed voids with various size, density and depth. The results obtained from the IR microscopy measurements give an overview of the techniques capability to detect and measure voids as well as some of its limitations.
Citation: Journal of Micro/Nanolithography, MEMS, and MOEMS
Pub Type: Journals
three dimensional stacked integrated circuits (3D-IC, 3DS-IC), wafer bond, bond void metrology, infrared (IR) microscopy