We report the fabrication and characterization of double-gated Si nanowire field effect transistors with excellent current-voltage characteristics, low subthreshold slope ~ 85 mV/dec and high on/off current ratio ~ 10^6. The Si nanowire devices are fabricated by using a self-aligned technique with standard photolithographic alignment and metal lift-off processes, enabling the large-scale integration of high-performance nanowire devices. We have also studied the effect of device structure and forming gas rapid thermal annealing on the nanowire transistors electrical properties. We conclude that the self-aligned fabrication and non-overlapped gate-source/drain structure combined with appropriate post annealing leads to the excellent observed device performance.
Proceedings Title: Proceedings of the 8th IEEE International Conference on Nanotechnology
Conference Dates: August 18, 1996-August 21, 2008
Conference Location: Arlington, TX
Conference Title: The 8th IEEE International Conference on Nanotechnology
Pub Type: Conferences
Nanoelectronics, Sii-nanowires, field-effect transistors, subthreshold