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Controlled Formation and Resistivity Scaling of Nickel Silicide Nanolines

Published

Author(s)

Bin Li, Zhiquan Luo, Paul S. Ho, Li Shi, Lew Rabenberg, JiPing Zhou, Richard A. Allen, Michael W. Cresswell

Abstract

We demonstrate a top-down method to fabricate nickel mono-silicide (NiSi) nanolines with smooth side walls and linewidths down to 15 nm. Four probe electrical measurements revealed that the electrical resistivity at room temperature remained constant as the line width reduced to 23 nm. The resistivity at cryogenic temperatures was found to increase with decreasing line width arising from electron scattering at the sidewall and yielded an electron mean free path of 6.3 nm for NiSi at room temperature. The results suggest that NiSi nanolines with smooth sidewalls can be used without degradation of device performance in nanoscale electronics at the 22 nm technology node.
Citation
Nanotechnology
Volume
20

Keywords

electron transport, nickel silicide, resistance, nano-lines, fabrication, surface scattering, phonon scattering, CD, linewidth

Citation

Li, B. , Luo, Z. , Ho, P. , Shi, L. , Rabenberg, L. , Zhou, J. , Allen, R. and Cresswell, M. (2009), Controlled Formation and Resistivity Scaling of Nickel Silicide Nanolines, Nanotechnology, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=32991 (Accessed May 26, 2024)

Issues

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Created February 24, 2009, Updated October 12, 2021