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Challenges of High-[kappa] Gate Dielectrics for Future MOS Devices

Published

Author(s)

John S. Suehle, Eric M. Vogel, Monica D. Edelstein, Curt A. Richter, Nhan Van Nguyen, Igor Levin, Debra Kaiser, Hanchang F. Wu, J B. Bernstein

Abstract

As the feature sizes of complementary metal-oxide-semiconductor (CMOS) devices are scaled downward, the gate dielectric thickness must also decrease to maintain a value of capacitance to reduce short-channel effects and to keep device drive current at an acceptable level. The Semiconductor Industry Association's (SIA) International Technology Roadmap for Semiconductors (ITRS) indicates thatby the years 2003-2005, the equivalent thickness of the gate dielectric will need to be approximately 1.5 nm. Reducing the thickness of SiO2 to these dimensions results in an exponential increase of direct tunneling current It has been suggested that SiO2 as thin as 1.6 nm may be tolerable in terms of intrinsic reliability and leakage for high performance applications. Although the exact thickness limit for SiO2 is debatable, at some technology node the use of SiO2 as the gate dielectric will no longer be possible. A suitable replacement gate dielectric with a high permittivity ([kappa]) must exhibit low leakage current, have the ability to be integrated into a CMOS process flow, and exhibit at least the same equivalent capacitance, performance, and reliability of SiO2. Many candidates of possible high-[kappa] gate dielectrics have been suggested to replace SiO2, as shown in Table 1. The purpose of this overview is to discuss the general requirements and challenges associated with these materials as possible gate dielectrics. Issues to be discussed include processing, dielectric constant, capacitance, bandgap, tunnel current, and reliability.
Proceedings Title
Proc., 2001 International Symposium on Plasma and Process-Induced Damage
Conference Dates
May 13-15, 2001
Conference Location
Monterey, CA, USA

Keywords

dielectrics, high-K gate dielectrics, MOS devices, MOS, CMOS, gate dielectric

Citation

Suehle, J. , Vogel, E. , Edelstein, M. , Richter, C. , Nguyen, N. , Levin, I. , Kaiser, D. , Wu, H. and Bernstein, J. (2001), Challenges of High-[kappa] Gate Dielectrics for Future MOS Devices, Proc., 2001 International Symposium on Plasma and Process-Induced Damage, Monterey, CA, USA (Accessed December 7, 2023)
Created May 12, 2001, Updated October 12, 2021