The Challenge of Measuring Defects in Nanoscale Dielectrics
Kin P. Cheung, John S. Suehle
Defects in nanoscale gate dielectric of MOS devices can exchange charges with the substrate via quantum mechanical tunneling. This characteristic has been utilized in many measurement methods to measure the defects and its spatial distribution. In some cases, the quantitative relationship between tunneling time and defect depth can be established. In other cases, this is not yet possible due to the lack of knowledge about the interface trap-fill time. As gate dielectrics reaches less than 1 nm equivalent oxide thickness, the measurement techniques must be made at higher speeds. Measurement into the GHz range will be needed.
213th ECS meeting: Dielectrics for Nanosystems
May 19-22, 2008
213th Meeting of the Electrochemical Society
CMOS, defect, gate dielectric, nano, trap-fill time, charge-pumping, noise