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The Challenge of Measuring Defects in Nanoscale Dielectrics

Published

Author(s)

Kin P. Cheung, John S. Suehle

Abstract

Defects in nanoscale gate dielectric of MOS devices can exchange charges with the substrate via quantum mechanical tunneling. This characteristic has been utilized in many measurement methods to measure the defects and its spatial distribution. In some cases, the quantitative relationship between tunneling time and defect depth can be established. In other cases, this is not yet possible due to the lack of knowledge about the interface trap-fill time. As gate dielectrics reaches less than 1 nm equivalent oxide thickness, the measurement techniques must be made at higher speeds. Measurement into the GHz range will be needed.  
Proceedings Title
213th ECS meeting: Dielectrics for Nanosystems
Conference Dates
May 19-22, 2008
Conference Location
Phoenix, AZ
Conference Title
213th Meeting of the Electrochemical Society

Keywords

CMOS, defect, gate dielectric, nano, trap-fill time, charge-pumping, noise

Citation

Cheung, K. and Suehle, J. (2008), The Challenge of Measuring Defects in Nanoscale Dielectrics, 213th ECS meeting: Dielectrics for Nanosystems, Phoenix, AZ (Accessed May 30, 2024)

Issues

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Created May 26, 2008, Updated February 19, 2017