Published: September 01, 2017
Quentin Smets, Anne S. Verhulst, Eddy Simoen, David J. Gundlach, Curt A. Richter, Nadine Collaert, Marc Heyns
The tunnel-FET (TFET) is a promising candidate for future low-power logic applications because it enables a sub-60 mV/dec subthreshold swing. However, most experimental TFETs are plagued by unwanted trap-assisted tunneling (TAT) and Shockley-Read-Hall (SRH) generation currents, which degrade the swing and increase the leakage floor, hence forming a major roadblock for TFET adoption. It is still unclear which type of traps causes this degradation. In this letter, we calibrate TAT and SRH caused by bulk traps with the help of In0.53Ga0.47As p+/n+ and p+/i/n+ diodes on lattice matched substrates. Using these calibrated models, we then make performance predictions for an In0.53Ga0.47As TFET. We find that the bulk SRH and TAT currents are sufficiently low compared to the target off-state current and hence not a significant issue. Therefore it is likely that the degradation commonly observed in experimental In0.53Ga0.47As TFETs on lattice matched substrates is not caused by bulk semiconductor defects, but by semiconductor/oxide interface defects.
Citation: IEEE Electron Device Letters
Pub Type: Journals
nanoelectronics, tunnel-FETs, TFET, tunnel diode, low-energy computing, Shockley-Read-Hall, SRH
Created September 01, 2017, Updated September 11, 2017