Skip to main content
U.S. flag

An official website of the United States government

Official websites use .gov
A .gov website belongs to an official government organization in the United States.

Secure .gov websites use HTTPS
A lock ( ) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.

Bonded Wafers for Three-Dimensional Integration

Published

Author(s)

Richard A. Allen

Abstract

Three-dimensional (3D) integration is a key enabling technology for compact, high-performance, and/or low-power electronics. This technology enables the fabrication of circuits with functions that commonly cannot be fabricated on a single substrate in a smaller 3D footprint, a key consideration in portable and wearable devices, or can enable higher density of transistors in a 3D footprint, a key consideration in high-performance computing. 3D stacking, in turn, is enabled by wafer bonding, whereby two or more wafers are bonded into a single “device”, which can then be inserted into a system.
Citation
SEMI Standards Watch

Keywords

there-dimesional stacked integrated circuits (3DS-IC), packaging, integrated circuits

Citation

Allen, R. (2017), Bonded Wafers for Three-Dimensional Integration, SEMI Standards Watch, [online], http://www.semi.org/en/node/120011?utm_source=hs_email&utm_medium=email&utm_content=43758623&_hsenc=p2ANqtz-_c81n0SMz3VgUwguZfM_gPwa8ObHwxmCNfXfXWTAgUnTOREQFBbhMpKj5KOFjHSWv_Chof_pkqpKiViAWjfGBE1kYnHA&_hsmi=43758623 (Accessed June 22, 2024)

Issues

If you have any questions about this publication or are having problems accessing it, please contact reflib@nist.gov.

Created March 2, 2017, Updated October 5, 2017