Martin, A.
, Suehle, J.
, Chaparala, P.
, O'Sullivan, P.
, Mathewson, A.
and Messick, C.
(1996),
Assessing MOS Gate Oxide Reliability on Wafer Level with Ramped/Constant Voltage and Current Stress, 1995 IEEE International Integrated Reliability Workshop Final Report, Lake Tahoe, CA, USA
(Accessed May 9, 2025)
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
Secure .gov websites use HTTPS
A lock (
) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.
Assessing MOS Gate Oxide Reliability on Wafer Level with Ramped/Constant Voltage and Current Stress
Published
Author(s)
A. Martin, , P Chaparala, P. O'Sullivan, A. Mathewson, C. Messick
Proceedings Title
1995 IEEE International Integrated Reliability Workshop Final Report
Conference Dates
October 22-25, 1995
Conference Location
Lake Tahoe, CA, USA
Pub Type
Conferences
Citation
Issues
If you have any questions about this publication or are having problems accessing it, please contact reflib@nist.gov.
Created December 30, 1996, Updated October 12, 2021