Overlay Metrology Using Physics and AI-Based Scanning Electron Microscopy

Description

Overview

The project aims to build a complete, physics-backed metrology pipeline for deployment in commercial semiconductor chip fabrication facilities and research labs to optimize scanning electron microscopy (SEM)-based overlay, critical dimensions (CD), and defect inspection. Beyond production applications, this work helps establish foundational physical and documentary measurement standards. Findings and technology will be actively transferred to the semiconductor industry through technical presentations, direct technology exchanges, and collaborative meetings with chipmakers.

Background 

Fabricating semiconductor chips involves building multiple intricate circuit layers on top of one another. Every layer must align with absolute precision; even a sub-nanometer misalignment can render a chip non-functional. Verifying this alignment—a process known as overlay metrology—is one of the most vital quality assurance steps in semiconductor manufacturing. However, as chips scale down while integrating many billions of components, conventional dimensional measurement techniques are reaching their limits. Meeting atomic-scale alignment requirements demands next-generation measurement tools that deliver unprecedented speed and accuracy.

This project creates an advanced overlay metrology solution by pairing Scanning Electron Microscopy (SEM) with physics-based computer simulations and artificial intelligence (AI). The primary goal is to create measurement methods that can verify layer to layer alignment in chips with the precision required by modern and future manufacturing processes.

A key project objective is to determine the detection limits of AI-based SEM dimensional metrology. The AI models used in this work have varying performance characteristics and thus unique detection limits. By determining these limits, the project team will enable semiconductor vendors and AI model consumers to understand and trust the measurements produced by AI-based SEM dimensional metrology.

Approach

Atomic-level overlay and critical dimension measurements are essential for the process control needed by U.S. integrated circuit manufacturing. By integrating physical simulations directly with AI, the project enhances every step of the measurement workflow.

Key technical efforts include:

• Advanced Simulations: Expanding high-speed Monte Carlo simulation software on the NIST computing cluster to model overlay target performance.
• Methodology Benchmarking: Comparing traditional inspection techniques against model-based overlay measurements.
• Throughput Optimization: Testing sparse-scanning image acquisition to accelerate the identification and measurement of overlay structures.
• AI Integration: Implementing AI algorithms for image acquisition, noise reduction, and detailed feature analysis in SEM overlay images.
• System Integration: Delivering an end-to-end SEM overlay metrology framework designed for present and future industry needs, supported by active industry collaboration through a Cooperative Research and Development Agreement (CRADA).

Impact

High-throughput, atomic-resolution overlay and CD measurements are crucial for maintaining strict process control in chip manufacturing. Combining physics modeling with AI will drive the development of more powerful scanning electron microscopes.

To this end, the project will (1) define the precise performance limits of AI-driven SEM overlay and CD metrology; (2) improve measurement speed and accuracy across semiconductor production processes; and (3) establish essential design parameters to guide the development of purpose-built SEM systems for CD, overlay, and related dimensional metrology. For NIST, this research yields state-of-the-art measurement capabilities—enabling highly accurate atomic-scale imaging through advanced AI models, rapid image simulations, and precise, physics-based 3D reconstructions of feature size, shape, and placement.

Expected Outcomes

The project aims to build a complete, physics-backed metrology pipeline for deployment in commercial chip fabrication facilities and research labs to optimize SEM-based overlay, CD, and defect inspection. Beyond production applications, this work helps establish foundational physical and documentary measurement standards. Findings and technology will be actively transferred to the semiconductor industry through technical presentations, direct technology exchanges, and collaborative meetings with chipmakers.

Resources 

• Code Repository: github.com/usnistgov/chips-overlay-metrology

Created September 3, 2026, Updated September 18, 2026