The wide distribution of ON and OFF values and high SET current in resistive memory is attributed to the high current overshoot during the SET process. In this paper we show a circuit which is capable of precisely limiting the current during SET process. The circuit can achieve an overshoot free SET current as low as 20 µA within 500 ps. This results in less than 200 µA of device RESET current while maintaining a relatively large RON/ROFF ratio greater than 104.
Proceedings Title: ECS FAll Meeting Trasnsaction
Conference Dates: October 7-12, 2012
Conference Location: Honolulu, HI
Conference Title: ECS Fall Meeting 2012
Pub Type: Conferences