Circuit Speed Timing Jitter Increase in Random Logic Operation after NBTI Stress

Published

June 1, 2014

Author(s)

Guangfan Jiao, Jiwu Lu, Jason Campbell, Jason Ryan, Kin P. Cheung, Chadwin D. Young, Gennadi Bersuker

Abstract

Recently, much effort has been spent trying to relate NBTI observations to real circuit impacts. While many of these efforts rely on circuit simulation to bridge this gap, an experimental approach is, of course, preferred. In this study we provide this experimental solution in the form of eye-diagram measurements to quantify NBTI-induced changes in timing jitter. We investigate these NBTI-induced jitter increases using a variety of ring-oscillator as well as pseudo-random gate patterns. The pseudo-random gate pattern is a close approximation to real world random logic. We observe that the NBTI-induced jitter increase depends strongly on the chosen gate pattern and is most severe for the pseudo-random case. These observations strongly suggest that more regular gate pattern (ring-oscillator) measurements underestimate the circuit impact of NBTI.

Proceedings Title

Proceedings of the IEEE International Reliability Physics Symposium

Conference Dates

June 1-5, 2014

Conference Location

Waikoloa, HI, US

Pub Type

Conferences

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Keywords

Negative bias temperature instability (NBTI), pseudo-random bit sequence (PRBS), eye diagram, jitter

Citation

Jiao, G. , Lu, J. , Campbell, J. , Ryan, J. , Cheung, K. , Young, C. and Bersuker, G. (2014), Circuit Speed Timing Jitter Increase in Random Logic Operation after NBTI Stress, Proceedings of the IEEE International Reliability Physics Symposium, Waikoloa, HI, US, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=915921 (Accessed October 25, 2025)