Impact-Ionization-Based High-Endurance One-Transistor Bulk CMOS Cryogenic Memory

Published

March 31, 2025

Author(s)

Pragya Shrestha, Alexander Zaslavsky, Valery Ortiz Jimenez, Jason Campbell, Curt Richter

Abstract

This paper presents a high-endurance capacitorless one-transistor (1T) cryogenic memory, fabricated in a 180 nm bulk CMOS technology, with a high memory window of (107 I1/I0 sense current ratio) and prolonged retention. The memory is enabled by the bistable ID–VG transistor characteristics due to impact ionization (II) at cryogenic temperatures (T < 30 K). Focusing on critical memory reliability parameters—switching time, endurance, and retention characteristics—we present write/erase speeds down to ≈ 45 ns at T < 10 K and cycling endurance surpassing 10⁹ cycles while maintaining the I1/I0 memory window. Retention times of >10 s with a 30 X memory window were observed in extensive high-speed measurements. The fast switching and retention characteristics combine to yield a low power (µW-range) candidate for local cache memory to support a quantum sensing or quantum computing control circuitry. Additionally, our study outlines essential measurements crucial for exploring the viability of alternative memory solutions for low-temperature quantum sensing and computation applications.

Citation

IEEE Journal of the Electron Devices Society

Volume

13

Pub Type

Journals

Download Paper

https://doi.org/10.1109/JEDS.2025.3552036

Local Download

Keywords

Impact ionization, cryogenic memory, switching time, memory endurance, memory retention, cryogenic cMOS

Citation

Shrestha, P. , Zaslavsky, A. , Ortiz Jimenez, V. , Campbell, J. and Richter, C. (2025), Impact-Ionization-Based High-Endurance One-Transistor Bulk CMOS Cryogenic Memory, IEEE Journal of the Electron Devices Society, [online], https://doi.org/10.1109/JEDS.2025.3552036, https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=957733 (Accessed May 24, 2025)