Device-Level Jitter as a Probe of Ultrafast Traps in High-k MOSFETs

Published

April 16, 2016

Author(s)

Dmitry Veksler, Jason Campbell, Kin Cheung, J. Zhong, H. Zhu, C. Zhao

Abstract

A methodology for evaluation of ultra-fast interfacial traps, using jitter measurements as a probe, is developed. This methodology is applied to study the effect of PBTI stress on density of ultra-fast electron traps (with 500ps to 5ns characteristic capture/emission times) in a high-k/Si nMOSFET. It is shown that in spite of observed increase of timing jitter after PBTI stress, this increase may not be associated with growing density of interface traps, but is solely caused by a VT shift, which simply decreases the output signal amplitude. The results indicate that ultra-fast (presumably interface) traps may not be affected by PBTI stress.

Proceedings Title

proceedings of 2016 IEEE International Reliability Physics Symposium

Conference Dates

April 17-21, 2016

Conference Location

Pasadena, CA, US

Conference Title

2016 IEEE International Reliability Physics Symposium

Pub Type

Conferences

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Keywords

Dit, jitter, high-K MOS, Interface characterization.

Citation

Veksler, D. , Campbell, J. , Cheung, K. , Zhong, J. , Zhu, H. and Zhao, C. (2016), Device-Level Jitter as a Probe of Ultrafast Traps in High-k MOSFETs, proceedings of 2016 IEEE International Reliability Physics Symposium, Pasadena, CA, US, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=920496 (Accessed September 30, 2025)