2023 SPIE Advanced Lithography and Patterning Symposium

Remarks as prepared.

It is a true pleasure to be able to join all of you here today.

In a speech last week, Secretary Raimondo laid out the vision for the nation to unleash the next generation of American innovation, protect our national security, and preserve our global economic competitiveness as we implement the historic CHIPS Act. Today, I want to talk to you about where we are in that implementation.

Just to level set and remind people of the funding that we have to carry out this vision, Congress created two categories of incentives that Commerce is implementing — the manufacturing incentives and the R&D incentives.

Thirty-nine billion in manufacturing incentives is targeted at bringing back manufacturing of semiconductor chips to the U.S. Eleven billion is budgeted to create the R&D ecosystem that will keep those companies here in the U.S. to support that next discovery and great advancement that will keep the U.S. in a lead position globally.

NIST was selected as the bureau to be the home for CHIPS because of its deep technical expertise, industry focus, experience with public-private partnerships, and strong administrative functions.

As you know, the Department of Defense and other agencies have also received CHIPS funding; and we are working with those initiatives.

Today, I’ll be focusing on the CHIPS for America program at the National Institute of Standards and Technology.

It has been an intense six months since the passage of the CHIPS Act, and as a result of all of this work that includes extensive outreach and engagement with the community, you will see several key announcements out of the CHIPS program in the next month.

Funding Opportunities

Let me start by talking about the manufacturing incentives portion of the program — the $39 billion investment to bring semiconductor manufacturing and the associated supply chain back to the U.S.

I am happy to announce that the first CHIPS for America Notice of Funding Opportunity will be released tomorrow.  

This first Notice of Funding Opportunity (NOFO) seeks applications for incentives to construct, expand or modernize commercial facilities for leading-edge, current-generation and mature-node semiconductors. This includes both front-end fabrication and back-end packaging. We are focusing this first announcement in order to bolster the chip manufacturing capability and capacity that we know is critical to our country’s economic and national security.  

Now, while the first funding opportunity is directed toward chipmakers, we know the broader semiconductor supply chain and R&D efforts are essential to creating a competitive ecosystem for semiconductor manufacturing. Therefore, in the late spring, we plan to release another funding opportunity focused on materials suppliers and equipment manufacturers.

And in the early fall, we plan to announce a funding opportunity to support the construction of semiconductor R&D facilities that will further strengthen the U.S. semiconductor ecosystem.  

Each funding announcement will provide the detailed processes and timelines that entities need to apply for CHIPS incentives.  

Now, if you qualify for ANY of these three funding opportunities, you will be able to file a statement of interest with Commerce upon release of the first NOFO tomorrow.

Therefore, it is important for suppliers and equipment manufacturers and those entities interested in building out R&D capacity to look at the first NOFO. We will provide everyone across the semiconductor supply chain the opportunity to submit a short Statement of Interest to inform us of anticipated interest in CHIPS incentives funding. 

And this will be critically important for us to determine the needs of this part of the industry and plan for the second and third NOFO.

We want to start hearing from everybody when we announce the first funding opportunity.

Tomorrow’s funding announcement contains:

• Program objectives and priorities,
• Funding instruments,
• How to apply, and
• Application evaluation and selection processes.

It will be available at CHIPS.gov.

But we will also be releasing additional resources for applicants at the same time as or close to the funding announcement, and these resources will include:

• Vision for success document where we outline our strategic priorities for the manufacturing incentives funding,
• Workforce development guide to help inform applicant workforce plans, and
• Frequently asked questions and answers.

As with everything else, these will be available at CHIPS.gov.

Program Priorities

I want to go into some specifics regarding the NOFO tomorrow as this is the first time we have talked about it publicly.  

Specifically, this funding opportunity seeks applications that demonstrate, first and foremost, the ability to bolster our economic and national security. Therefore, we seek to invest in projects that meaningfully increase U.S. semiconductor production, with a particular emphasis on projects that will mitigate risks from supply chain shocks associated with the geographic concentration of current semiconductor production. We will also consider whether projects meet the government’s need for access to safe, secure and domestically produced chips. 

We need to see evidence of commercial viability. Applications should demonstrate an understanding of:

• Risks and mitigation strategies for the project, 
• Product demand and customers and, if possible, should include customer commitments, and
• The useful life of the facility and necessary investments to prevent obsolescence.

With respect to financial strength, applicants should structure the finances of their project in a way that maximizes private-sector contributions and minimizes the need for government incentives. When we do this right, we are catalyzing private investment, not replacing it. 

We need to see evidence of project technical feasibility and readiness. Applicants should provide a clear project execution plan and demonstrate readiness to meet environmental and permitting requirements. Importantly, we encourage projects that leverage state and local incentives.

In the area of workforce development, applicants should provide plans to develop the construction workforce and the technical workforce and do this in an inclusive way.

And finally, broader impacts: We are interested in how projects will make a difference in areas like research and development, opportunities for small businesses, environmental stewardship, and community vitality. 

In the next few slides, I want to talk in a little more detail about a few of these — economic resilience and national security, which is critically important for the success of this program; workforce development; and what we mean by broader impacts.

As I mentioned, we are seeking to invest in projects that meaningfully increase U.S. semiconductor production and strengthen U.S. supply chains.

For leading-edge facilities, we are seeking projects that utilize the most advanced technology. This funding will be focused not only on the next wave of U.S.-based production, but on establishing a virtuous cycle of investment and innovation that reestablishes U.S. leadership in the semiconductor industry. As such, we will evaluate the extent to which the applicant makes credible commitments of ongoing investment in the United States.

For current-generation and mature-node facilities, we are seeking projects that support production of semiconductors critical to our economic resilience, such as semiconductors used in automobiles, aerospace and defense, medical devices or critical infrastructure sectors. 

In order to increase U.S. resilience to potential supply shocks, we will also generally favor proposals to build foundry capacity that can serve a range of customers. 

We also seek to invest in back-end production facilities. In particular, we seek to secure U.S. leadership in advanced packaging, which will be critical to leadership in leading-edge logic technology and manufacturing. 

In reviewing applications, we will also consider whether a project furthers the national security interests of the United States. This includes the provision of stable, long-term onshore access to semiconductor technologies for government organizations and their contractors. We are committed to supporting projects that meet government agencies’ need for access to safe, secure and domestically produced chips. 

Moreover, we seek projects with the ability to adapt commercial production, testing and packaging models for low-volume national security components or otherwise apply commercial technologies to meet specific national security and whole-of-government objectives. 

In addition, according to the CHIPS statute, no funds made available under this section may be used to construct, modify or improve a facility outside of the United States.

A highly skilled, diverse workforce is critical to meeting the goals of the CHIPS Incentives Program. This includes both the construction workforce who build or expand facilities, and the semiconductor workforce who operate them. Applicants are required to provide a workforce development plan that covers both construction and facility needs.

For construction workers, each applicant will be required to submit a construction workforce plan to recruit, hire, train and retain a diverse and skilled construction workforce. 

For the facilities workforce, each applicant must also create a workforce development plan to articulate the applicant’s approach to meeting their facility workforce needs.

Each applicant should commit to appropriate investments to recruit, train, hire and retain workers in good jobs at their facility.

Recruiting, training and retaining a diverse and skilled set of workers will necessitate building new pipelines for workers, including specific efforts to attract economically disadvantaged individuals.

Each applicant should make efforts to co-lead or participate in partnerships for workforce development, and these strategic partners can include: 

• Educational institutions (including four-year universities, and community and technical colleges), 
• Training organizations,
• Government organizations, 
• Economic development organizations, 
• Workforce development organizations, 
• Labor unions, 
• Industry associations, 
• Community-based organizations, and 
• Career technical education organizations for students in public K-12 schools and community colleges.  

And finally, because child care is critical to expanding employment opportunity for economically disadvantaged individuals, the CHIPS program requires that any applicant requesting Direct Funding over $150 million provide access to affordable child care for facility and construction workers.

CHIPS for America is committed to building strong communities that participate in the prosperity of the semiconductor industry, as well as ensuring that taxpayer investments maximize benefits for the U.S. economy. 

In particular, we are interested in how projects will create broader impacts across the following dimensions: 

• We seek to prioritize incentives for applicants that are committed to future investments that grow the domestic semiconductor industry including continued reinvestment. 
• Applicants for CHIPS incentives should help ensure that the semiconductor R&D innovation ecosystem can flourish. Therefore, we are asking applicants to commit to participating in the CHIPS R&D programs that I will discuss in a minute.
• Applicants should explain how they will address creating inclusive opportunities for businesses; and strong applications will include proactive steps to do so.
• Applicants are expected to design their projects to minimize the potential for adverse impacts on the environment and the local community, and will be asked to submit a climate and environmental responsibility plan. 
• And finally, in the area of community investments, applicants should strive to ensure that their investments contribute to a region’s long-term strategy for economic vitality. For example, if transit costs are a significant barrier to attracting workers, investments that reduce those costs can help unlock a region’s potential for long-term growth, while simultaneously promoting equity.

Funding Instruments and Application Process

There are three types of CHIPS incentives: 

1. Direct funding, which provides funding to the applicant for eligible costs and can take the form of grants, cooperative agreements, or other transactions,
2. Loans, which are direct loans from the federal government to the applicant for eligible costs, and
3. Loan guarantees, which are federal guarantees of third-party loans to the applicant for eligible costs. 

Incentives will be specifically negotiated and tailored to every recipient, potentially with a mix of loans, loan guarantees and direct funding.

The application process will have five parts: 1) Statement of Interest, 2) an optional Pre-Application, 3) Full Application, 4) Due Diligence, and 5) Award Preparation.

Review of applications will be an iterative and negotiated process, tailored for every single application, and designed to produce the best proposals. We are building a cross-cutting team of experts who will review applications on a rolling basis as they are submitted.

The review teams will consist of people with industry expertise, financial, investment and tax experience, and knowledge of risk management as well as a regulatory and legal teams. The teams will also include subject matter experts in guardrails, environmental compliance, community investment, workforce development, national security and other critical policy matters related to CHIPS for America implementation. 

Funding decisions will be targeted and strategic to catalyze private sector investment and maximize the impact of every public dollar spent. 

Research and Development

Now I will provide more detail on developments in the CHIPS for America Research and Development arm.

The NIST CHIPS Act R&D Programs will address five cross-cutting issues that we identified through extensive interaction with members of industry, academia and other government agencies.

1. Access to facilities and equipment for late-stage R&D and prototyping: Currently, there is a need for a centralized, open-access facility or facilities that are equipped with fabrication tools, testing and expertise relevant to a manufacturing environment for prototyping leading-edge technologies. 
2. Advanced packaging and testing: Advanced packaging includes more than one chip in a traditional package, and sometimes a variety of chip types having a wide range of functions in a 3D arrangement, all mounted on a substrate. And as we all know this area is ripe for innovation. As advanced packaging, assembly, and testing is done predominantly by companies in Asia, this puts the U.S. at a disadvantage. 
3. Advanced metrology: Industry stakeholders have told us that they need measurement science to progress to enable the development of advanced nodes, three-dimensional devices and other leading-edge technologies. Measurement science advances are needed across the semiconductor development landscape from raw materials to manufacturing process steps to advanced packaging.
4. Manufacturing technology: Much of cutting-edge manufacturing will occur at the nanometer scale — even at the atomic scale for some elements, as leading-edge features shrink below 10 nm. Further scaling requires the development of more sophisticated manufacturing processes and tools with unprecedented precision. Virtualization and simulation of wafer production will aid in scaling up, as will improved automation of manufacturing processes and materials handling and logistics.
5. Workforce development: Recently announced fabs and the CHIPS Act incentives will create a huge demand for workforce talent. The R&D programs will create training opportunities for STEM students to prepare them for careers in the semiconductor industry.

To address those ecosystem gaps, as you have seen, CHIPS for America will invest in four overlapping entities, all of which include some aspect of workforce training. 

• National Semiconductor Technology Center 
• National Advanced Packaging Manufacturing Program 
• Manufacturing USA institute(s)
• National Institute of Standards and Technology R&D

These programs will share infrastructure, participants and projects. They will operate in coordination with each other, with the CHIPS for America manufacturing incentives program, and with microelectronics R&D programs supported by other U.S. federal agencies, including the Microelectronics Commons investments by DoD. 

All being designed concurrently, and connected together working with recommendations from the community through RFI, workshops, the industrial advisory committee, PCAST and other sources, including visits with CEOs of large and small companies.

We are working diligently to coordinate with interagency partners — DOD, DOE, NSF — to make sure our investments are coordinated and not competing.

The National Semiconductor Technology Center 

The NSTC is a multibillion-dollar investment and is envisioned as the anchor for the CHIPS R&D program.

The NSTC will be a public-private consortium that provides a platform where government, industry, customers, suppliers, educational institutions, entrepreneurs, workforce representatives and investors converge to address the semiconductor ecosystem’s most pressing challenges and opportunities.

As specified by statute, the NSTC will develop a comprehensive semiconductor research and development program that will include research funding, prototyping capabilities, an investment fund and workforce development programs. The Industrial Advisory Committee is helping to think through gaps and grand challenges that will excite and stimulate R&D across the U.S. through this entity.

We anticipate the creation of an independent entity with NSTC leadership reporting to a governing board informed and advised by indus¬try, academia, government and key stakeholders. 

We are currently searching for a CEO for the entity that will operate National Semiconductor Technology Center (NSTC). 

We will publish an NSTC white paper in March 2023 that will provide guidance on the design and process for standing up the NSTC. 

National Advanced Packaging Manufacturing Program

Advanced packaging is the current state of the art, but the U.S. has little to no capacity for advanced packaging at present.

It is cost prohibitive to bring conventional packaging back to the U.S. — but we have an opportunity to skip ahead to advanced packaging capabilities as they are developing worldwide.

If we do not develop the expertise for advanced packaging, the U.S. will cede leadership in semiconductor design and manufacturing to other countries. 

The National Advance Packaging Manufacturing program is also a multibillion dollar program as designated in the law. The NSTC and Manufacturing USA will work closely together, and we anticipate a single point of entry for many programs. We also anticipate that the NSTC will operate any pilot facilities associated with the advanced packaging program.

Some likely areas of focus for this funding based on input from the community include co-design and simulation, chiplets, a pilot packaging plant, tooling and automation, and research on materials and substrates.

NIST Metrology R&D

This several hundred million dollar program will be primarily funding NIST research and development in advanced measurement science and metrology tools. However, we almost always do our cutting-edge research in partnership and will be seeking academic and industrial partners for this work as well. 

NIST has been working with the semiconductor industry since its inception and will push forward new measurement capabilities in this program working closely with industry.

Research will include measurement science and characterization technologies to enable the development of advanced nodes, three-dimensional devices and other leading-edge technologies. 

We will conduct the measurement science critical to the development of new materials and packaging, and develop physical metrology for next-generation microelectronics, including 3D devices for logic and memory and 3D heterogeneous integration/advanced packaging.

We will develop computation methods and tools for data validation; develop tools for virtualization and automation; create reference materials and reference data, and calibrations; and contribute to the development of standards for processes, cybersecurity and test methods.

Manufacturing USA Institutes

The CHIPS for America R&D program will also leverage the Manufacturing USA model to help bridge the gap from research to commercialization.

Manufacturing USA is a network of regional institutes that convene businesses, academia and other stakeholders to test applications of new technology, create new products, reduce cost and risk, and enable the manufacturing workforce with the skills of the future. 

Currently, 16 institutes serve a variety of sectors, from biopharma and biomanufacturing, to composites, to digital manufacturing and robotics, to energy, sensors and flexible electronics.  

In this several hundred million dollar program, NIST will establish one, and up to three, new institutes focused on semiconductors.

Eight of these current institutes intersect with the semiconductor industry, and we are discussing ways to fund coordinated projects and programs across the relevant partners in the network.

Real-World Integration

So how does all this programming and collaboration come together in the real world? Let’s just take a look at the integration of the NAPMP packaging program and the NSTC.

We envision the NSTC to be the centerpiece of the program — an independent operator managing multiple sites and assets with unique capabilities for prototyping and research. We also envision that the NSTC will run key parts of the packaging program — the packaging pilot plant and chiplets program. We envision that the packaging program will also separately invest in research in materials and substrates and new tool design and new metrology. But in the creation of IP in the chiplet area or in packaging in general, we will make this IP accessible to partners across the CHIPS R&D program.

Let me give you a hypothetical. Imagine that a large automotive company — a member of the NSTC — is building a 3D platform for autonomous driving. The project is highly aligned with NSTC capabilities, so NSTC provides most of the support. 

The company would move faster with a proven 3D platform from a prior Department of Defense Commons project, some technology from the NAPMP chiplet library, and access to NAPMP advanced packaging processes. In this hypothetical, NSTC would coordinate access to these technologies.

After prototyping to a high technology readiness level, the technology enters a domestic foundry for high-volume manufacturing as a commercial technology. The technology is now also available to inspire new ideas for both the commercial and defense sectors.

The main takeaway is that by coordination and sharing of resources, programs across the U.S. government can greatly expand the amount of technology, expertise and capacity available to developers. These factors will increase the chance of success of a new technology, and help reduce the cost and time to market.

This is just one example of how CHIPS for America will make a difference. 

If we get this right, and we plan to, both the incentives and R&D programs will be transformational for this country. The long-term payoff will be reestablishing this sector as an engine of innovation for the U.S. domestic economy.  

NIST and the Department of Commerce are excited by this challenge, and are already hard at work. There is room for everyone to participate, and for all of us to benefit.