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Tailoring the High-K Gate Dielectric/Sillicon Interface for CMOS Applications

Published

Author(s)

Y S. Lin, R Puthenkovilakam, J P. Chang, C P. Bouldin, Igor Levin, Nhan Van Nguyen, Y Sun, P Pianetta, T Conard, W Vandervorst, V Venturo, S Selbrede

Abstract

The interfacial properties, thermal stabilities, and the electrical characteristics of ZrO2/ Si and ZrO2/SiO2/Si were investigated and the interfacial layer of as-deposited ZrO2 on silicon is likely to be ZrSixOy. The ZrO2/ZrSixOy/Si is stoichiometic, uniform, amorphous, and has an equivalent oxide thickness of difference} 1.3 nm and a dielectric constant of 20.5 with leakage current of 3.2 x 10-3 A/cm2 at 1.5V. the as-deposited ZrO2/ZrSixOy/Si film stack is thermally stable up to 880 C and its thermally stability improved to 925 C upon oxygen or ammonia annealing. After oxygen annealing, the interfacial layer showed a more SiO2 like character and the interfacial layer thickness increased by 1 nm. In addition, the overall dielectric constant was reduced to 15.7. For NH3 annealing, ZrO2 underwent nitridation and the interfacial layer thickness increased by 0.6 nm with the overall dielectric constant reduced to 12.9.
Citation
Applied Physics

Keywords

characterization, high-K gate diectrics, interface, tunable, zirconium oxide

Citation

Lin, Y. , Puthenkovilakam, R. , Chang, J. , Bouldin, C. , Levin, I. , Nguyen, N. , Sun, Y. , Pianetta, P. , Conard, T. , Vandervorst, W. , Venturo, V. and Selbrede, S. (2021), Tailoring the High-K Gate Dielectric/Sillicon Interface for CMOS Applications, Applied Physics (Accessed May 20, 2022)
Created October 12, 2021