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Single electron tunnelling transistor with tunable barriers using silicon nanowire MOSFET

Published

Author(s)

Akira Fujiwara, Hiroshi Inokawa, Kenji Yamazaki, Hideo Namatsu, Yasuo Takahashi, Neil M. Zimmerman, Stuart Martin

Abstract

Single-electron tunnelling (SET) transistors1 are now of great and wide interest as basic elements for future applications such as low-power nanoelecronics2 and read-out electrometer for solid-state quantum computing3. Silicon SET devices4 have great potential because such applications inevitably rely on integration capability and stable operation5. We report the operation of SET transistors with tunable barriers using silicon nanowire MOSFET structures that are now intensively studied for next-generation CMOS. We demonstrate tuning the conductance of tunnel barriers by more than three orders of magnitude. By using this flexible control of the barriers, we can have various configurations of charge islands in a single device; we observed the systematic evolution from a single island to double islands. Also, in spite of a number of efforts to fabricated silicon SET transistors, no work has achieved sufficient controllability in device parameters. We obtained excellent reproducibility in the gate capacitances: values on the order of 10aF, with the variation smaller than 1aF. This flexibility and controllability both demonstrates that the device is highly designable to build a variety of SET devices based on CMOS technology.
Citation
Applied Physics Letters
Volume
88
Issue
053121-1

Keywords

SET transistors, silicon, tunable barriers

Citation

Fujiwara, A. , Inokawa, H. , Yamazaki, K. , Namatsu, H. , Takahashi, Y. , Zimmerman, N. and Martin, S. (2006), Single electron tunnelling transistor with tunable barriers using silicon nanowire MOSFET, Applied Physics Letters, [online], https://doi.org/10.1063/1.2168496 (Accessed May 20, 2024)

Issues

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Created March 6, 2006, Updated October 12, 2021