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A Simple Series Resistance Extraction Methodology for Advanced CMOS Devices



Jason P. Campbell, Kin P. Cheung, John S. Suehle, A Oates


Series resistance has become a serious obstacle inhibiting the performance of advanced CMOS devices. However, series resistance quantification in these same advanced CMOS devices is becoming exceedingly difficult. In this study, we demonstrate a very simple series resistance extraction procedure which is derived from the ratio of two linear ID-VG measurements. This approach has a verifiable accuracy check and is successfully used to extract the series resistance from several advanced devices. Furthermore, the validity of the assumptions used in this series resistance extraction procedure are examined and shown to be justified. In an attempt to further test the validity of this technique, several known external resistors were inserted in series with the device under test. The series resistance extraction procedure faithfully reproduces these known external resistances.
IEEE Electron Device Letters


Campbell, J. , Cheung, K. , Suehle, J. and Oates, A. (2011), A Simple Series Resistance Extraction Methodology for Advanced CMOS Devices, IEEE Electron Device Letters (Accessed April 21, 2024)
Created August 1, 2011, Updated February 19, 2017