A Simple Series Resistance Extraction Methodology for Advanced CMOS Devices

Published

August 1, 2011

Author(s)

Jason P. Campbell, Kin P. Cheung, John S. Suehle, A Oates

Abstract

Series resistance has become a serious obstacle inhibiting the performance of advanced CMOS devices. However, series resistance quantification in these same advanced CMOS devices is becoming exceedingly difficult. In this study, we demonstrate a very simple series resistance extraction procedure which is derived from the ratio of two linear ID-VG measurements. This approach has a verifiable accuracy check and is successfully used to extract the series resistance from several advanced devices. Furthermore, the validity of the assumptions used in this series resistance extraction procedure are examined and shown to be justified. In an attempt to further test the validity of this technique, several known external resistors were inserted in series with the device under test. The series resistance extraction procedure faithfully reproduces these known external resistances.

Citation

IEEE Electron Device Letters

Volume

32

Issue

8

Pub Type

Journals

Citation

Campbell, J. , Cheung, K. , Suehle, J. and Oates, A. (2011), A Simple Series Resistance Extraction Methodology for Advanced CMOS Devices, IEEE Electron Device Letters (Accessed June 6, 2023)