Practical High-Resolution Programmable Josephson Voltage Standards using Double- and Triple-Stacked MoSi2 -Barrier Junctions

Published

June 1, 2005

Author(s)

Yonuk Chong, Charles J. Burroughs, Paul Dresselhaus, Nicolas Hadacek, Hirotake Yamamori, Samuel Benz

Abstract

We have developed vertically stacked superconductor-normal metal- superconductor Josephson junction technology for the next generation quantum voltage standards. Stacked junctions provide a practical way of increasing the output voltage and operating margins. In this paper, we present fully functioning programmable voltage standard chips with double- and triple-stacked MoSi₂ barrier Josephson junctions with over 100,000 junctions operating simultaneously on a 1 cm 'e 1 cm chip. The maximum output voltages of the double- and triple-stacked chips were 2.6 V and 3.9 V, with respective operating current margins of 2 mA and 1 mA. A new trinary-logic design is used to achieve higher voltage resolution. Thermal transport in these high-density chips will be briefly discussed.

Citation

IEEE Transactions on Applied Superconductivity

Volume

15

Issue

2

Pub Type

Journals

Download Paper

Local Download

Keywords

Josephson arrays, Programmable voltage standard, Superconducting integrated circuits, Superconductor- normal-superconductor devices

Citation

Chong, Y. , Burroughs, C. , Dresselhaus, P. , Hadacek, N. , Yamamori, H. and Benz, S. (2005), Practical High-Resolution Programmable Josephson Voltage Standards using Double- and Triple-Stacked MoSi₂ -Barrier Junctions, IEEE Transactions on Applied Superconductivity, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=31816 (Accessed October 7, 2024)