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Power dissipation in a vertically integrated chip-scale atomic clock

Published

Author(s)

John Kitching, Svenja A. Knappe, Li-Anne Liew, P Schwindt, V Shah, John Moreland, Leo W. Hollberg

Abstract

The physics package of a vertically-integrated chip-scale atomic clock based on Cs has recently been demonstrated at NIST. This device requires 69 mW of electrical power to maintain the vapor cell 34 K above the temperature of the baseplate. The physics package structure is analyzed using analytical thermal modeling and finite-element calculation. Improvements to the design are proposed to reduce the power consumption of the physics package alone to below 15 mW and of a full chip-scale atomic clock to below approximately 30 mW. Power consumption at this level will open the door to the use of atomic frequency references in portable, battery-operated applications such as wireless communications and global positioning.
Proceedings Title
Proc. IEEE Intl. Ultrasonics, Ferroelectrics, and Frequency Control Anniversary Joint Conf.
Conference Dates
August 24-27, 2004
Conference Location
Montreal, 1, CA
Conference Title
IEEE Intl. Ultrasonics, Ferroelectrics, and Frequency Control Conf.

Keywords

atomic clock, compact frequency reference, MEMS, micromachining, VCSEL

Citation

Kitching, J. , Knappe, S. , Liew, L. , Schwindt, P. , Shah, V. , Moreland, J. and Hollberg, L. (2004), Power dissipation in a vertically integrated chip-scale atomic clock, Proc. IEEE Intl. Ultrasonics, Ferroelectrics, and Frequency Control Anniversary Joint Conf., Montreal, 1, CA, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=50085 (Accessed July 19, 2024)

Issues

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Created August 23, 2004, Updated October 12, 2021