PBTI-Induced Random Timing Jitter in Circuit-Speed Random Logic

Published

November 13, 2014

Author(s)

Jiwu Lu, Canute I. Vaz, Guangfan Jiao, Jason P. Campbell, Jason T. Ryan, Kin P. Cheung, Gennadi Bersuker, Chadwin D. Young

Abstract

Accurate reliability predictions of real world digital logic circuits rely heavily on the relevancy of device level testing. In the case of bias temperature instability (BTI), where recovery plays a significant role, a leap of faith is taken to translate device level reliability data into practical information for the real world circuit implications. In this work, we develop a methodology to bridge this gap by employing an eye diagram approach which allows us to monitor, at circuit speed, device level random jitter degradation in response to stress. By employing a variety of positive BTI (PBTI) gate voltage stress and sense bit sequences (including DC, ring oscillator, and pseudo random), we are able to compare the effectiveness of these approaches at capturing random timing jitter. We find that conventional ring oscillator type measurements are unable to capture the random jitter degradation. This calls into question the effectiveness of using ring oscillator structures as a proxy to real random logic circuits. Only when a pseudo random bit sequence is employed does the true extent of jitter degradation become observable. This is an important development and serves as an accurate means to translate device level reliability data to predict real world digital logic circuit degradation.

Citation

IEEE Transactions on Electron Devices

Pub Type

Journals

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Keywords

PBTI, Jitter, PRBS

Citation

Lu, J. , Vaz, C. , Jiao, G. , Campbell, J. , Ryan, J. , Cheung, K. , Bersuker, G. and Young, C. (2014), PBTI-Induced Random Timing Jitter in Circuit-Speed Random Logic, IEEE Transactions on Electron Devices, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=915964 (Accessed September 11, 2024)