Skip to main content
U.S. flag

An official website of the United States government

Official websites use .gov
A .gov website belongs to an official government organization in the United States.

Secure .gov websites use HTTPS
A lock ( ) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.

Parasitic engineering for RRAM control

Published

Author(s)

Pragya R. Shrestha, David M. Nminibapiel, Dmitry Veksler, Jason P. Campbell, Jason T. Ryan, helmut Baumgart, Kin P. Cheung

Abstract

The inevitable current overshoot which follows forming or switching of filamentary resistive random access memory (RRAM) devices is often perceived as a source of variability that should be minimized. This sentiment has resulted in efforts to curtail the overshoot by decreasing the parasitic capacitance using highly integrated 1T-1R or 1R-1R device structures. While this is readily achievable in single device test structures, it poses an intricate constraint for memory array designs. Several reports suggest that, for small parasitic capacitances and/or low current compliance levels, there is insufficient current to form stable filaments. Thus, the relationship between minimizing overshoot current and improved filament stability is tenuous. In this study, we utilize the forming energy-based understanding of filamentary switching to show that the parasitic capacitance should be optimized, rather than minimized for better filament control.
Citation
Solid State Electronics
Volume
150

Keywords

current overshoot, forming, resistive random access memory (RRAM), switching variability

Citation

Shrestha, P. , Nminibapiel, D. , Veksler, D. , Campbell, J. , Ryan, J. , Baumgart, H. and Cheung, K. (2018), Parasitic engineering for RRAM control, Solid State Electronics, [online], https://doi.org/10.1016/j.sse.2018.10.006 (Accessed October 26, 2021)
Created October 15, 2018, Updated February 8, 2019