Metrology requirements for next generation of semiconductor devices

Published

April 4, 2019

Author(s)

Ndubuisi G. Orji

Abstract

Although devices based on traditional CMOS architectures are expected to reach their physical limits in the next few years, the devices and materials involved are more complex and difficult to measure than ever before. The nanoscale sizes mean that the same fundamental limitations that will affect device performance also affect available metrology methods. In addition to nanoscale size and complex structure, next generation devices will incorporate new materials such as graphene and transition metal dichalcogenide films. Because of changes in materials properties, measurements of film thickness and other parameters will require considerably more information about the layer-dependent material properties. This could be challenging for existing metrology techniques. The presentation will outline some of the key materials and lithography metrology challenges and highlight promising new techniques in an era of not only increased complexity, but one where scaling is no longer the main industry driver.

Conference Dates

April 2-4, 2019

Conference Location

Monterrey, CA

Conference Title

Frontiers of Characterization and Metrology for Nanoelectronics (FCMN)

Pub Type

Conferences

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Keywords

Semiconductor metrology, gate all around, 3D VLSI

Citation

Orji, N. (2019), Metrology requirements for next generation of semiconductor devices, Frontiers of Characterization and Metrology for Nanoelectronics (FCMN), Monterrey, CA, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=927435 (Accessed April 23, 2024)