Metrology Needs for TSV Fabrication

Published

March 4, 2014

Author(s)

Victor H. Vartanian, Richard A. Allen, Larry Smith, Klaus Hummler, Steve Olson, Brian Sapp

Abstract

This paper focuses on the metrology needs and challenges of through silicon via (TSV) fabrication, consisting of TSV etch, liner, barrier, and seed (L/B/S) depositions, copper plating, and copper CMP. These TSVs, with typical dimensions within a factor of two or so of 5 micrometers x 50 micrometers (diameter x depth) present a new set of metrology challenges because of the high aspect ratio and large feature sizes. The metallization deposition process includes thin layers of liner, barrier metal, and seed metal; metrology for these layers ensures that there is complete coverage of the sidewalls, providing electrical isolation from the wafer. Metrology for the fill step includes verifying that the TSVs are deposited without voids, and that the extent of stress on the surrounding silicon does not exceed acceptable limits.

Citation

Journal of Micro/Nanolithography, MEMS, and MOEMS

Volume

13

Issue

1

Pub Type

Journals

Keywords

through silicon via (TSV), three dimensional stacked integrated circuits (3D-IC, 3DS-IC), metrology

Citation

Vartanian, V. , Allen, R. , Smith, L. , Hummler, K. , Olson, S. and Sapp, B. (2014), Metrology Needs for TSV Fabrication, Journal of Micro/Nanolithography, MEMS, and MOEMS (Accessed December 10, 2023)