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Lack of charge offset drift is a robust property of Si single electron transistors



Emmanouel S. Hourdakis, J A. Wahl, Neil M. Zimmerman


Single electron transistors (SETs) face several challenges before they can be considered technologically useful devices. One of them is the random, low frequency, charge offset drift that inhibits their use in parallel. Recently, tunable barrier Si SETs were shown to have a drift of only 0.01 e over several days. Those devices all came from one fabrication source. Here, we present the results for tunable barrier Si SET fabricated by our group (a different fabrication source). We demonstrate their operation as SETs. We show clear Coulomb oscillations as well as a clear diamond diagram . Finally, we confirm the fact that the charge offset drift is less than 0.01 e, which is comparable to the previous study of Si SETs and orders of magnitude better than metal ones, demonstrating the lack of charge offset drift is generic to Si devices, and not dependent on the fabrication source.
Applied Physics Letters


charge offset drift, Coulomb blockage, Si devices, single-electron transistor


Hourdakis, E. , Wahl, J. and Zimmerman, N. (2008), Lack of charge offset drift is a robust property of Si single electron transistors, Applied Physics Letters, [online],, (Accessed June 15, 2024)


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Created February 11, 2008, Updated October 12, 2021