Impact of Measurement Setup on Cryogenic CMOS FET Characterization

Published

March 31, 2026

Author(s)

Pragya Shrestha, Jason Campbell, Jhih-Wei Chen, Mau-Chung Frank Chang

Abstract

Accurate cryogenic device characterization is essential for developing compact models to support scalable quantum control electronics based on advanced CMOS nodes. However, we show that abnormal I–V characteristics observed in 16 nm and 28 nm devices at cryogenic temperatures arise from not only from intrinsic device behavior, but also self-sustained oscillations induced by parasitic LC feedback in standard measurement setups. These effects are exacerbated at low temperatures due to increased device gain and especially prominent in configurations with lossless high-inductance. SPICE simulations incorporating realistic parasitics, combined with high-resolution time-domain measurements, confirm the presence of these oscillations and their impact on time-averaged DC values. We demonstrate that using ground-signal-ground (GSG) RF probes effectively suppresses these artifacts by minimizing loop inductance, restoring true device behavior. These results highlight the need for careful test structure and setup design to ensure reliable cryogenic CMOS characterization.

Citation

IEEE Electron Device Letters

Volume

47

Issue

6

Pub Type

Journals

Download Paper

https://doi.org/10.1109/LED.2026.3679453

Local Download

Keywords

cryogenic CMOS, measurement induced artifacts, device characterization

Citation

Shrestha, P. , Campbell, J. , Chen, J. and Chang, M. (2026), Impact of Measurement Setup on Cryogenic CMOS FET Characterization, IEEE Electron Device Letters, [online], https://doi.org/10.1109/LED.2026.3679453, https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=961170 (Accessed May 29, 2026)

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