Impact ionization-induced bistability in CMOS transistors at cryogenic temperatures for capacitorless memory applications
Alexander Zaslavsky, Curt A. Richter, Pragya Shrestha, Brian Hoskins, Son Le, Advait Madhavan, Jabez J. McClelland
Cryogenic operation of complementary metal oxide semiconductor (CMOS) silicon transistors is crucial for quantum information science, but it brings deviations from standard transistor operation. Here we report on sharp current jumps and stable hysteretic loops in the drain current as a function of gate voltage VG for both n-type and p-type commercial-foundry 180-nm-process CMOS transistors when operated at voltages exceeding 1.3 V at cryogenic temperatures. The physical mechanism responsible for the device bistability is impact ionization (II) charging of the transistor body, which leads to effective back-gating of the inversion channel. This mechanism is verified by independent measurements of the body potential. The hysteretic loops, which have a >107 ratio of high to low drain current states at the same VG, can be used for compact capacitorless single-transistor memory at cryogenic temperatures with long retention times.
, Richter, C.
, Shrestha, P.
, Hoskins, B.
, Le, S.
, Madhavan, A.
and McClelland, J.
Impact ionization-induced bistability in CMOS transistors at cryogenic temperatures for capacitorless memory applications, Applied Physics Letters, [online], https://doi.org/10.1063/5.0060343, https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=932731
(Accessed August 12, 2022)