Impact ionization-induced bistability in CMOS transistors at cryogenic temperatures for capacitorless memory applications

Published

July 29, 2021

Author(s)

Alexander Zaslavsky, Curt A. Richter, Pragya Shrestha, Brian Hoskins, Son Le, Advait Madhavan, Jabez J. McClelland

Abstract

Cryogenic operation of complementary metal oxide semiconductor (CMOS) silicon transistors is crucial for quantum information science, but it brings deviations from standard transistor operation. Here we report on sharp current jumps and stable hysteretic loops in the drain current as a function of gate voltage VG for both n-type and p-type commercial-foundry 180-nm-process CMOS transistors when operated at voltages exceeding 1.3 V at cryogenic temperatures. The physical mechanism responsible for the device bistability is impact ionization (II) charging of the transistor body, which leads to effective back-gating of the inversion channel. This mechanism is verified by independent measurements of the body potential. The hysteretic loops, which have a >107 ratio of high to low drain current states at the same VG, can be used for compact capacitorless single-transistor memory at cryogenic temperatures with long retention times.

Citation

Applied Physics Letters

Volume

119

Issue

4

Pub Type

Journals

Download Paper

https://doi.org/10.1063/5.0060343

Local Download

Keywords

cryogenic CMOS, bistability, impact ionization, capacitorless memory, quantum engineering

Citation

Zaslavsky, A. , Richter, C. , Shrestha, P. , Hoskins, B. , Le, S. , Madhavan, A. and McClelland, J. (2021), Impact ionization-induced bistability in CMOS transistors at cryogenic temperatures for capacitorless memory applications, Applied Physics Letters, [online], https://doi.org/10.1063/5.0060343, https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=932731 (Accessed April 26, 2024)