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IC Test Structures for Multi-Layer Interconnect Stress Determination
Published
Author(s)
S. A. Smee, Michael Gaitan, Donald B. Novotny, Yogendra K. Joshi, David L. Blackburn
Abstract
A new method for measuring strain in multi-layer IC interconnects is presented. This method utilizes process compatible micromachined test structures and is applied to the determination of longitudinal interconnect stress in a standard dual-metal-layer CMOS process. Strain measurements are shown to be consistent for an array of similar test structures, and stress values, calculated from constitutive relations, are in good agreement with published results.
Citation
IEEE Electron Device Letters
Volume
21
Issue
1
Pub Type
Journals
Keywords
CMOS, IC, interconnect, micromachined, strain, stress, test structures
Citation
Smee, S.
, Gaitan, M.
, Novotny, D.
, Joshi, Y.
and Blackburn, D.
(2000),
IC Test Structures for Multi-Layer Interconnect Stress Determination, IEEE Electron Device Letters
(Accessed October 11, 2025)