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Fabrication, characterization and simulation of high performance Si nanowire-based non-volatile memory cells

Published

Author(s)

Xiaoxiao Zhu, Qiliang Li, D. E. Ioannou, Xuelei X. Liang, Diefeng Gu, Helmut Baumgart, John E. Bonevich, John S. Suehle, Curt A. Richter

Abstract

We report the fabrication, characterization and simulation of Si nanowire SONOS-like non- volatile memory with HfO2 charge trapping layers of varying thicknesses. The memory cells, which are fabricated by self-aligning in situ grown Si nanowires, exhibit high performance, i.e. fast program/erase operations, long retention time and good endurance. The effect of the trapping layer thickness of the nanowire memory cells has been experimentally measured and studied by simulation. As the thickness of HfO2 increases from 5 to 30 nm, the charge trap density increases as expected, while the program/erase speed and retention remain the same. These data indicate that the electric field across the tunneling oxide is not affected by HfO2 thickness, which is in good agreement with simulation results. Our work also shows that the Ω gate structure improves the program speed and retention time for memory applications.
Citation
Nanotechnology

Keywords

Silicon Nanowire, Hafnium Oxide, SONOS, Nanoelectronics

Citation

Zhu, X. , Li, Q. , Ioannou, D. , Liang, X. , Gu, D. , Baumgart, H. , Bonevich, J. , Suehle, J. and Richter, C. (2011), Fabrication, characterization and simulation of high performance Si nanowire-based non-volatile memory cells, Nanotechnology, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=905507 (Accessed July 6, 2022)
Created May 15, 2011, Updated October 12, 2021