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Evaluation of New In-Chip and Arrayed Line Overlay Target Designs



M P. Davidson, M R. Bishop, Robert D. Larrabee, Michael T. Stocker, Jay S. Jun, Egon Marx, Richard M. Silver, Ravikiran Attota


Two types of overlay targets have been designed and evaluated for the study of optical overlay metrology. They are in-chip and arrayed overlay targets. In-chip targets are three-bar two-level targets designed to be placed in or near the active device area of a chip. They occupy a small area in the range of 5 ¿m2 to 15 ¿m2 and have line widths, which are nominally device dimensions. The close proximity of the line features result in strong proximity effects. We have used two well-established theoretical models to simulate and study the effects of proximity on overlay measurements. In this paper, we also present a comparison of optical overlay results with scanning electron microscope measurements. Arrayed targets have also been designed to improve and enhance the optical signal for small critical dimension features. We have also compared theoretical simulations of arrayed targets to experimental results. In these comparisons we observe a significant variation in the location of the best focus image with respect to the features. The through-focus focus-metric we have implemented in the current work to determine the best focus image shows interesting properties with potential applications for line width metrology and process control. Based on simulation results, the focus-metric is sensitive to changes in line width dimensions on the nanometer scale.
Proceedings Title
Proceedings of SPIE
Conference Dates
February 23, 2004
Conference Location
Santa Clara, CA, USA
Conference Title
Metrology, Inspection, and Process Control for Microlithography XVIII, Richard M. Silver, Editor, May 2004, Overlay and Registration Metrology II


best focus, CD metrology, focus metric, in-chip overlay targets, optical interaction, overlay metrology, proximity effect


Davidson, M. , Bishop, M. , Larrabee, R. , Stocker, M. , Jun, J. , Marx, E. , Silver, R. and Attota, R. (2004), Evaluation of New In-Chip and Arrayed Line Overlay Target Designs, Proceedings of SPIE, Santa Clara, CA, USA (Accessed May 27, 2024)


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Created May 23, 2004, Updated October 12, 2021