Design and Capabilities of the Assistive Clock Fusion Testbed
The National Institute of Standards and Technology (NIST) has been working with industry and academia to develop algorithms and technologies to improve the resilience of timing subsystems used in high-performance sensing and control hardware. Resilience improvements may include improved cybersecurity of the communicated time code, high quality local oscillators with better holdover properties and better time transfer protocols incorporating advanced modeling of the transfer channel. A major class of these techniques rely on a fusion of multiple time transfer methods and clocks where significant testing and optimization is needed to prove their efficacy. In order to test these fusion methods and evaluate them, a clock fusion testbed has been designed and built via contract. This device is intended to support software algorithms, DSP FPGA code as well as some low-level frequency synthesis techniques. Called the "Assistive Clock Fusion Testbed", the device includes all the basic components of hardware and comes pre-loaded with a reference implementation of simple fusion algorithm implemented on a hybrid SoC. This document outlines the design of the system and discusses an example use case where the device is used to combine the frequencies generated by two oven-controlled crystal-oscillators to produce a synthesized reference frequency compliant with the wander limits specified in the ITU-T G.8262 (SyncE) standard. The device features discussed cover the most generic configuration of the system. Some potential extensions and configurations for the device suited to more specific experiments and performance tests related to timing resilience are discussed at the end of the document.
Design and Capabilities of the Assistive Clock Fusion Testbed, Technical Note (NIST TN), National Institute of Standards and Technology, Gaithersburg, MD, [online], https://doi.org/10.6028/NIST.TN.2138
(Accessed August 1, 2021)