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Advait Madhavan (Assoc)

Advait Madhavan is a UMD Faculty Specialist in the Alternative Computing Group in the Nanoscale Device Characterization Division of the Physical Measurement Laboratory (PML). He received a Ph.D. in Electrical and Computer Engineering from the University of California, Santa Barbara and is  currently working with Mark Stiles and Jabez McClelland. His interests lie in various brain inspired approaches to computation such as temporal, analog and stochastic codes. His expertise lies in VLSI, with the objective of  building chips to interface with emerging technologies in order to realize these unconventional computing paradigms.

Selected Publications

  • Race logic: Abusing hardware race conditions to perform useful computation, Madhavan, A., Sherwood, T., & Strukov, D., EEE Micro: Micro's Top Picks from Computer Architecture Conferences35(3), 48-57 (2015).
  • Race logic: A hardware acceleration for dynamic programming algorithms, Madhavan, A., Sherwood, T., & Strukov, D., ACM SIGARCH Computer Architecture News42(3), 517-528 (2014).
  • A 4-mm 2 180-nm-CMOS 15-Giga-cell-updates-per-second DNA sequence alignment engine based on asynchronous race conditions, Madhavan, A., Sherwood, T., & Strukov, D., In Custom Integrated Circuits Conference (CICC), 2017 IEEE (pp. 1-4). IEEE (2017, April).

Publications

A System for Validating Resistive Neural Network Prototypes

Author(s)
Brian Hoskins, Mitchell Fream, Matthew Daniels, Jonathan Goodwill, Advait Madhavan, Jabez J. McClelland, Osama Yousuf, Gina C. Adam, Wen Ma, Muqing Liu, Rasmus Madsen, Martin Lueker-Boden
Building prototypes of heterogeneous hardware systems based on emerging electronic, magnetic, and photonic devices is an increasingly important area of research

Temporal Memory with Magnetic Racetracks

Author(s)
Hamed Vakili, Mohammed N. Sakib, Samiran Ganguly, Mircea Stan, Matthew Daniels, Advait Madhavan, Mark D. Stiles, Avik W. Ghosh
Race logic is a relative timing code that represents information in a wavefront of digital edges on a set of wires in order to accelerate dynamic programming
Created August 15, 2019, Updated June 15, 2021