Skip to main content

NOTICE: Due to a lapse in annual appropriations, most of this website is not being updated. Learn more.

Form submissions will still be accepted but will not receive responses at this time. Sections of this site for programs using non-appropriated funds (such as NVLAP) or those that are excepted from the shutdown (such as CHIPS and NVD) will continue to be updated.

U.S. flag

An official website of the United States government

Official websites use .gov
A .gov website belongs to an official government organization in the United States.

Secure .gov websites use HTTPS
A lock ( ) or https:// means you’ve safely connected to the .gov website. Share sensitive information only on official, secure websites.

Advait Madhavan (Fed)

Advait Madhavan is a UMD Assistant Research Scientist in the Alternative Computing Group in the Nanoscale Device Characterization Division of the Physical Measurement Laboratory (PML). He received a Ph.D. in Electrical and Computer Engineering from the University of California, Santa Barbara and is currently working with Mark Stiles and Jabez McClelland. His interests lie in various brain inspired approaches to computation such as temporal, analog and stochastic codes. His expertise lies in VLSI, with the objective of building chips to interface with emerging technologies in order to realize these unconventional computing paradigms.

Selected Publications

  • Madhavan, Advait, Matthew W. Daniels, and Mark D. Stiles. "Temporal state machines: Using temporal memory to stitch time-based graph computations." ACM Journal on Emerging Technologies in Computing Systems (JETC) 17.3 (2021): 1-27.
  • Race logic: A hardware acceleration for dynamic programming algorithms, Madhavan, A., Sherwood, T., & Strukov, D., ACM SIGARCH Computer Architecture News42(3), 517-528 (2014).
  • A 4-mm 2 180-nm-CMOS 15-Giga-cell-updates-per-second DNA sequence alignment engine based on asynchronous race conditions, Madhavan, A., Sherwood, T., & Strukov, D., In Custom Integrated Circuits Conference (CICC), 2017 IEEE (pp. 1-4). IEEE (2017, April).

Publications

Patents (2018-Present)

The matrix decomposition system block.

Quasi-Systolic Processor and Quasi-Systolic Array

NIST Inventors
Matthew Daniels , Mark D. Stiles and Advait Madhavan
The invention is a computer architecture that efficiently calculates a weight matrix update for an AI model, especially ones designed to be implemented in hardware neural networks. Our architecture uses an approximation algorithm to do this calculation with less memory overhead. The architecture

Timing-Based Computer Architecture Systems And Methods

NIST Inventors
Advait Madhavan , Mark D. Stiles and Matthew Daniels
Tropical algebra is an emerging field of mathematics concerned with graph theory, control theory, and certain optimization problems, especially in discrete event systems. We developed a novel computer circuit called a tropical state machine that uses signal timing and the physics of nanodevices to
Created August 15, 2019, Updated December 9, 2022
Was this page helpful?