Design, Fabrication, and Characterization of High-Performance Silicon Nanowire Transistors

Published

August 1, 2008

Author(s)

Qiliang Li, Xiaoxiao Zhu, Yang Yang, D. E. Ioannou, Hao Xiong, John S. Suehle, Curt A. Richter

Abstract

We report the fabrication and characterization of double-gated Si nanowire field effect transistors with excellent current-voltage characteristics, low subthreshold slope 85 mV/dec and high on/off current ratio 10^6. The Si nanowire devices are fabricated by using a self-aligned technique with standard photolithographic alignment and metal lift-off processes, enabling the large-scale integration of high-performance nanowire devices. We have also studied the effect of device structure and forming gas rapid thermal annealing on the nanowire transistor's electrical properties. We conclude that the self-aligned fabrication and non-overlapped gate-source/drain structure combined with appropriate post annealing leads to the excellent observed device performance.

Proceedings Title

Proceedings of the 8th IEEE International Conference on Nanotechnology

Conference Dates

August 18, 1996-August 21, 2008

Conference Location

Arlington, TX, US

Conference Title

The 8th IEEE International Conference on Nanotechnology

Pub Type

Conferences

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Keywords

Nanoelectronics, Sii-nanowires, field-effect transistors, subthreshold

Citation

Li, Q. , Zhu, X. , Yang, Y. , Ioannou, D. , Xiong, H. , Suehle, J. and Richter, C. (2008), Design, Fabrication, and Characterization of High-Performance Silicon Nanowire Transistors, Proceedings of the 8th IEEE International Conference on Nanotechnology, Arlington, TX, US, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=33199 (Accessed October 12, 2025)