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Magnetic memory accelerates combinatorial optimization

Published

Author(s)

Hantao Zhang, William Borders, Mark Stiles

Abstract

Laying out computer chips, scheduling flights, and delivering packages are everyday optimization problems for which substantial financial benefits can be achieved by doing so as efficiently as possible. Li et al. [1] have taken an important step toward developing a platform based on novel hardware to solve such problems quickly and efficiently. The platform is based on a chip they fabricated with an integrated array of magnetic tunnel junctions designed to operate both quickly and with low energy consumption. They demonstrated this chip by solving model-optimization problems, such as those in chip layout.
Citation
Nature Electronics

Keywords

Magnetic tunnel junctions, optimization, chip layout, stochatic processes

Citation

Zhang, H. , Borders, W. and Stiles, M. (2026), Magnetic memory accelerates combinatorial optimization, Nature Electronics, [online], https://doi.org/10.1038/s41928-026-01713-1, https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=962658 (Accessed October 8, 2026)
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Issues

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Created September 9, 2026, Updated October 7, 2026
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