130-nm CMOS-Integrated Superparamagnetic Tunnel Junction-Based p-bit

Published

May 26, 2026

Author(s)

Nuno Cacoilo, Juyoung Yoon, Advait Madhavan, Jabez McClelland, Shun Kanai, Shunsuke Fukami, William Borders

Abstract

Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ's resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications.

Citation

IEEE Electron Device Letters

Volume

47

Issue

7

Pub Type

Journals

Download Paper

https://doi.org/10.1109/LED.2026.3696800

Local Download

Keywords

Nanofabrication, Probabilistic computing, magnetic tunnel junctions

Citation

Cacoilo, N. , Yoon, J. , Madhavan, A. , McClelland, J. , Kanai, S. , Fukami, S. and Borders, W. (2026), 130-nm CMOS-Integrated Superparamagnetic Tunnel Junction-Based p-bit, IEEE Electron Device Letters, [online], https://doi.org/10.1109/LED.2026.3696800, https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=960996 (Accessed July 7, 2026)

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