IP Security in Structured ASIC: Challenges and Prospects

Published

September 25, 2024

Author(s)

Rasheed Almawzan, Sudipta Paria, Aritra Dasgupta, Kostas Amberiadis, Swarup Bhunia

Abstract

With the globalization of hardware manufacturing and the growing demand for electronics, companies now heavily rely on offshore facilities for most of the design and manufacturing processes, including emerging technologies like Structured ASICs (Application Specific Integrated Circuits). This trend has prompted hardware designers to consider adopting a zero-trust model, acknowledging the possibility of malicious access to sensitive information at any stage of the design flow. Existing security solutions do not address these vulnerabilities for structured ASIC and are only designed to protect against limited attack surfaces. In this paper, we analyze the IP security issues in structured ASIC and discuss solutions to address them. We point to a layered approach for IP protection, where the unused resources in configurable logic blocks are utilized to minimize overhead costs.

Proceedings Title

2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

Conference Dates

July 1-3, 2024

Conference Location

Knoxville, TN, US

Pub Type

Conferences

Download Paper

https://doi.org/10.1109/ISVLSI61997.2024.00078

Local Download

Keywords

Hardware IP protection, Programmable Logic, ASIC, FPGA, Structured ASIC, Via Programmability, Reverse engineering, Hardware Trojans, Dark Silicon

Citation

Almawzan, R. , Paria, S. , Dasgupta, A. , Amberiadis, K. and Bhunia, S. (2024), IP Security in Structured ASIC: Challenges and Prospects, 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, TN, US, [online], https://doi.org/10.1109/ISVLSI61997.2024.00078, https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=957969 (Accessed October 16, 2025)