Large-Scale Integration of High-Performance Silicon Nanowire Field Effect Transistors

Published

September 16, 2009

Author(s)

Qiliang Li, Xiaoxiao Zhu, Yang Yang, D. E. Ioannou, Hao Xiong, Doowon Kwon, John S. Suehle, Curt A. Richter

Abstract

In this work we present a CMOS-compatible self-aligning process for the large-scale-integration of high performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on / off current ratio (> 107). The subthreshold swing is as small as 45 mV/dec which is substantially beyond the thermodynamic limit (60 mV/dec) of conventional planar MOSFETs. These excellent device characteristics are achieved by using a clean integration process and a device structure that allows effective gate-channel-source coupling to tune the source/drain Schottky barriers at the nanoscale.

Citation

Nanotechnology

Pub Type

Journals

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Keywords

nanoelectronics, nanowires, green electronics, field effect transistors

Citation

Li, Q. , Zhu, X. , Yang, Y. , Ioannou, D. , Xiong, H. , Kwon, D. , Suehle, J. and Richter, C. (2009), Large-Scale Integration of High-Performance Silicon Nanowire Field Effect Transistors, Nanotechnology, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=903269 (Accessed October 12, 2025)