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NSCI Seminar: Benchmarking Beyond CMOS Logic for Computation

Benchmarking of beyond-CMOS exploratory devices for logic integrated circuits is presented. It includes new devices with ferroelectric, piezoelectric, and orbitronic computational state variables. Standby power treatment and memory circuits are included. The benchmarking set of circuits is extended from logic gates up to sequential logic, including the Arithmetic Logic Unit which requires both logic and memory. The conclusion will show that Tunneling Field-Effect Transistors are the leading lowest energy-delay product option. Ferroelectric transistors may present an attractive option for non-volatile logic devices,  with faster switching delay. Among spintronics devices, magnetoelectric effects are more energy efficient than spin transfer torque, but switching speed of magnetization is a limitation. This benchmarking framework enables a better focus on promising beyond-CMOS exploratory devices.<?xml:namespace prefix = "o" ns = "urn:schemas-microsoft-com:office:office" /?>


NSCI Committee

1:00 p.m. - 2:00 p.m. (Gaithersburg, 101, Lecture Room B)

11:00 a.m. - 12:00 p.m. (Boulder, VTC in 81-1A116)

Ian Young

Created July 26, 2016, Updated July 29, 2016