Skip to main content
U.S. flag

An official website of the United States government

Dot gov

The .gov means it’s official.
Federal government websites often end in .gov or .mil. Before sharing sensitive information, make sure you’re on a federal government site.

Https

The site is secure.
The https:// ensures that you are connecting to the official website and that any information you provide is encrypted and transmitted securely.

RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level

Published

Author(s)

Miao (Tony) He, Jungmin Park, Adib Nahiyan, Apostol T. Vassilev, Yier Jin, Mark Tehranipoor

Abstract

Power side-channel attacks (SCAs) have become a major concern to the security community due to their non- invasive feature, low-cost, and effectiveness in extracting secret information from hardware implementation of cryto algorithms. Therefore, it is imperative to evaluate if the hardware is vulnerable to SCAs during its design and validation stages. Currently, however, there is little known effort in evaluating the vulnerability of a hardware to SCAs at early design stage. In this paper, we propose, for the first time, an automated framework, named RTL-PSC, for power side-channel leakage assessment of hardware crypto designs at register-transfer level (RTL) with built-in evaluation metrics. RTL-PSC first estimates power profile of a hardware design using functional simulation at RTL. Then it utilizes the evaluation metrics, comprising of KL divergence metric and the success rate (SR) metric based on maximum likelihood estimation to perform power side-channel leakage (PSC) vulnerability assessment at RTL. We analyze Galois- Field (GF) and Look-up Table (LUT) based AES designs using RTL-PSC and validate its effectiveness and accuracy through both gate-level simulation and FPGA results. RTL-PSC is also capable of identifying blocks∗ inside the design that contribute the most to the PSC vulnerability which can be used for efficient countermeasure implementation.
Proceedings Title
IEEE Transactions on Emerging Topics: VTS 2019
Conference Dates
April 23-25, 2019
Conference Location
Monterey, CA
Conference Title
IEEE VLSI Test Symposium 2019

Keywords

Side-channel Attacks, Leakage Assessment, Vulnerability Evaluation, Register-Transfer Level
Created July 11, 2019, Updated September 11, 2019