Roadmap on emerging hardware and technology for machine learning: Section 6 - Defectivity and its impact on hardware neural networks
Brian D. Hoskins, Matthew W. Daniels, Advait Madhavan, James A. Liddle, Jabez J. McClelland
The current state of the art in electronics manufacturing is driven by achieving low defect rates, high levels of device-to-device uniformity, and binning integrated circuits by quality. As the industry pushes digital logic to extremes below 5 nm in transistor channel length, new lithographic methods are needed to facilitate that scaling. Extreme ultra-violet (EUV) Lithography and directed self-assembly (DSA) are among such methods, but suffer from intrinsic limitations, such as stochastic photon illumination or assembly defects, respectively. These limitations push the defect rates to above the 0.01 cm-2 densities required for semiconductor manufacturing. Enabling logic to follow memory into the backend-of-line can relax feature- size-induced manufacturing problems. At the same time, this introduces new challenges in the 3D integration, particularly if similar areal densities are required. This is especially true in systems requiring new, CMOS compatible materials which suffer from defects that would be absent in single crystal silicon.
, Daniels, M.
, Madhavan, A.
, Liddle, J.
and McClelland, J.
Roadmap on emerging hardware and technology for machine learning: Section 6 - Defectivity and its impact on hardware neural networks, Nanotechnology, [online], https://doi.org/10.1088/1361-6528/aba70f
(Accessed December 5, 2021)