Overlay Metrology: Recent Advances and Future Solutions
Richard M. Silver, Jay S. Jun, S Fox, Edward A. Kornegay
As devices shrink and clock speeds continue to increase, process control and measurement of I critical dimension linewidths and the essential overlay of features from different photolithographic levels become increasingly important. Improved manufacturing control over level to level registration has a direct effect on device speed and yield. The measurement of level to level registration is called overlay metrology and is now recognized by the International Technical Roadmap for Semiconductors (ITRS) as one of the key metrology areas needed for improvement to maintain the historic pace of increasing device speeds and manufacturing economies of scale. The projected, required 3s repeatability of overlay measurements for the 100 nm generation devices is less than 4 nm. No known solutions are indicated in the roadmap for overlay repeatability better than 4 nm. In this article we will discuss the measurement of photolithographic registration and strategies to meet the ITRS goals through improved optical tool calibration and measurement techniques resulting in better measurement repeatability and accuracy.
Proccedings of Future Fab International
determination of the centerline, overlay, photolithographic 1evels, photolithographic registration, semiconductors