Negative Bias Temperature Instability of Deep Sub-Micron p-MOSFETs Under Pulsed Bias Stress

Published

October 21, 2002

Author(s)

Baozhong Zhu, John S. Suehle, Y Chen, J B. Bernstein

Abstract

Negative bias temperature instability (NBTI) and Positive bias temperature instability (PBTI) of p-MOSFETs with 2.4 nm thick oxide films were studied. The Δ}Vth interface trap generation of p-MOSFET at DC and AC bias stresses with frequency up to 500 KHz were measured. Additional tests were also conducted under unipolar and bipolar bias stresses with varied stress on and off times. The Δ}Vth and interface trap generation of p-MOSFET were observed to be significantly reduced for pulsed bias repetition frequencies greater than 10 KHz. however, Δ}Vth of PBTI was almost independent of the bias stress frequency. These results suggested that there are different mechanisms for NBTI and PBTI phenomena, and the reliability specifications of NBTI could possibly be relaxed under certain pulsed operation conditions.

Proceedings Title

Proc., Integrated Reliability Workshop

Conference Dates

October 21-24, 2002

Conference Location

Lake Tahoe, CA, USA

Conference Title

2002 Integrated Reliability Workshop

Pub Type

Conferences

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Keywords

frequency dependence, p-MOSFET, Negative bias temperature instability

Citation

Zhu, B. , Suehle, J. , Chen, Y. and Bernstein, J. (2002), Negative Bias Temperature Instability of Deep Sub-Micron p-MOSFETs Under Pulsed Bias Stress, Proc., Integrated Reliability Workshop, Lake Tahoe, CA, USA, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=30882 (Accessed October 27, 2025)