Chamberlin, R.
and Williams, D.
(2018),
Measurement and Modeling of Heterogeneous Chip-Scale Interconnections, IEEE Transactions on Microwave Theory and Techniques, [online], https://doi.org/10.1109/TMTT.2018.2873333
(Accessed December 14, 2024)
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Measurement and Modeling of Heterogeneous Chip-Scale Interconnections
Published
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Abstract
We present precision scattering-parameter measurements of chip-to-chip connections in heterogeneous integrated circuits: indium phosphide or gallium nitride chiplets mounted on SiCMOS carrier chips. We demonstrate methodology, experimental results, and modeling results of these chip- scale interconnections from DC to 110 GHz. We used Thru-Reflect-Line (TRL) on-wafer calibration to establish reference planes inside heterogeneous integrated circuits and then we translated those reference planes to the proximity of the chip-to-chip transitions to isolate their contribution to the scattering parameters.Citation
IEEE Transactions on Microwave Theory and Techniques
Volume
66
Issue
12
Pub Type
Journals
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Keywords
3-D heterogeneous integration and packaging, Thru-Reflect-Line (TRL) calibration, network analysis, indium phosphide, CMOS, gallium nitride.
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Created October 22, 2018, Updated April 15, 2019